Semiconductor package and flip chip bonding method therein

ABSTRACT

A semiconductor chip and an organic substrate are bonded together in an atmosphere having a reduced moisture content through Au bumps which have been subjected to a cleaning treatment therebetween. Using this bonding technique, a semiconductor chip and an organic substrate can be bonded together in a sufficiently high strength with use of Au bumps having a diameter of not larger than 300 μm, a height of not smaller than 50 μm, and a height/diameter ratio of not lower than 1/5, thus indicating a reduced strain.

TECHNICAL FIELD

[0001] The present invention relates to a semiconductor package having astructure wherein a semiconductor chip, such as an LSI chip, is mountedon a carrier substrate formed of an organic material.

BACKGROUND OF THE INVENTION

[0002] Heretofore, a method of connecting a semiconductor chip to asubstrate by a flip chip bonding technique, a method using solder bumpshas been known as a C4 technique. According to this method, solder bumpsare formed on chip-side Al electrode pads through a barrier metal, whileAu plating superior in solder wettability is applied to substrate-sideconnecting terminals, and a solder is caused to reflow in a fluxlessnon-oxidizing atmosphere to effect bonding of the chip to the substrate.In the case where the substrate being used is a ceramic substrate, thesubstrate is used as a hermetic sealing, while in the case of an organicsubstrate, a resin-silicon compound which has been adjusted to thethermal expansion coefficient is filled between a chip and resin toenhance the reliability of a soldered portion.

[0003] On the other hand, Au bump/Au pad flip chip bonding methodswithout using solder have been known, including a thermocompressionbonding method and a thermosonic bonding method. Conventional conditionsfor thermocompression bonding involve a heating temperature of 350° C.,a load of 150 to 250 g/bump, and the number of bumps on a chip of lessthan 50. Likewise, conventional conditions for thermosonic bondinginvolve a heating temperature of 200° C., a load of 300 g, and six bumpsor so on a chip. In both cases, a carrier substrate made of a ceramicmaterial is used. In thermocompression bonding, the load is lowered byraising the heating temperature, but a load of 150 g/bump is stillrequired. In thermosonic bonding, the heating temperature is reduced to200° C., but a load as high as 300 g/bump is still required. Theseconditions were found as a result of various studies made for attaininga positive Au/Au bond in the air. Lower temperature and lower loadconditions are not applicable to the actual product assembly because thebonding would become unstable. In both compression bonding methodsmentioned as above, the compression-bonded shape of an Au bump affords abonded portion of a largely crushed shape having a thickness of 15 to 25μm and a diameter of 150 μm or more as typical sizes.

[0004] Another conventional Au bump/Au pad connecting method is knownwherein both are subjected to compression bonding under heating with useof an electrically conductive resin as an adhesive which is interposedtherebetween. According to this method, resin is filled and solidifiedbetween a chip and a substrate, thereby attaining a predeterminedlong-term reliability.

[0005] With the development of an ultra-fine wiring technique, therecent LSI chips are becoming higher and higher in the degree ofintegration, and the pad pitch is becoming narrower rapidly as thenumber of pins on a chip increases or as with the chip reduced in size.In the case of mounting such a chip to a package, the conventionalperipheral pad bonding technique gives rise to two problems. That is, inTAB and wire bonding, a bondable pad pitch encounters a limit at a levelof 40 μm. Since wiring from a chip terminal to an external terminal ofthe package cannot be provided along the shortest route, the wiringinductance increases, causing a delay in signal transmission, and theprocessing speed decreases.

[0006] According to a method proposed to solve the above-mentionedproblems, electrode terminals of a chip are arranged areawise on thewhole surface of the chip. The solder bump bonding method (C4) alreadyemployed in the field of conventional large-sized computers can solvethe foregoing two problems, but when it is applied to a semiconductorpackage, there arises a problem concerning the soldering temperature.More particularly, in a large-sized computer, a high-melting solder(95Pb-5Sn solder melting at 300° C.) is used for soldering a chipbecause of the necessity for subsequent hierarchical soldering.Generally, a suitable soldering temperature is about 50° C. higher thanthe melting point of the solder being used, so that, when the substratematerial is not a ceramic, but is an organic material, it is impossibleto use such a high-melting solder because the substrate will undergo aheat deterioration. If a solder is used which has a solid phasetemperature in the range of 200° C. to 240° C., there will arise aproblem in that, in a eutectic soldering process for mounting asemiconductor package onto a wiring board, a soldered portion inside ofthe package partially melts again and causes a failure due to breakingof the wire. Thus, in the internal connection of a semiconductorpackage, a connection having a heat resistance of not lower than 250° C.must be realized while bonding at a low temperature of not higher than250° C.

[0007] A known bonding method suitable for this requirement is a flipchip bonding method using Au bumps. According to this bonding method,Au, which has a high melting point and is superior in bondability, isformed into a bump shape and compression bonding is performed in a solidphase by heating or by using an ultrasonic wave, thus permitting aheat-resistant bonded portion at a low bonding temperature. In theconventional Au bump bonding method, however, such a large bonding loadas 300 g per bump is required, and in the actual case of a chip having100 to 2,000 bumps, the load applied to the chip reaches 30 to 600 kg.Consequently, chipping or cracking of the chip caused by a localabutment of a pressing tool against the chip poses a serious problem.According to experiment, a maximum load applicable to the chip ispresumed to be in the range of about 20 to 40 kg, so that the actualapplication of the conventional bonding method is difficult unless ahighly reliable bonding can be performed at a bonding load of 20 g to 80g per bump. If the bonding temperature can be raised in the conventionalthermocompression bonding method, it is possible to effect a reliablebonding in a low load condition. However, since the substrate is formedof an organic material, the heating temperature cannot be raised above250° C. even for a polyimide having heat resistance and above 200° C.for use of an epoxy resin from the standpoint of avoiding heat damage.In a thermosonic bonding method capable of effecting a reliable bondingat a low heating temperature and a relatively low load, a highultrasonic energy is required for obtaining a reliable bonded portion,thus giving rise to the problem that the chip is damaged by ultrasonicoscillation. Further, both thermocompression bonding and ultrasoniccompression bonding afford a considerably crushed bump shape afterbonding, so that, as the pad pitch becomes as narrow as 200 μm or so dueto chip shrink, there arises a problem of a short-circuit with anadjacent pad due to bump deformation. At the same time, the spacingbetween adjacent bumps becomes 50 μm or so at a height of about 20 μm,so that when resin is filled, voids are apt to occur and the filling ofan under-fill resin becomes difficult, thus causing the problem ofdeterioration in reliability as a package.

[0008] On the other hand, the method using Au bumps and an electricallyconductive resin performs a compression bonding at a low heatingtemperature and a low bonding load as a bonding condition so that it ispossible to bond, diminishing the deformation of the bumps; and,besides, since the compression bonding in this method is performed afterpre-filling resin between a chip and a substrate in a connectingprocess, it is possible to assemble a good package free of voids.However, in the case of an electrically conductive resin, the state ofcontact of its conductive particles is deteriorated due to a cubicalexpansion caused by moisture absorption and there arises a problem inreliability that the resistance increases with the lapse of time.

[0009] Recently, as a measure for reducing the package cost, there hasbeen proposed a chip scale package of the type in which assembly to apackage is performed at the stage of wafer. For mounting a package to awiring board, there usually is adopted a structure wherein the packageis bonded to the wiring board through solder ball bumps. In this case,ensuring reliability without reinforcing the soldered portion with anunder-fill resin is important in terms of reducing the package mountingcost and ensuring repairability. To this end, it is necessary to adopt astructure in which a heat strain is relieved in a portion other than thesoldered portion so as to prevent the heat strain from beingconcentrated in the soldered portion, in which heat strain is generateddue to a difference between the thermal expansion coefficient of an Sichip and that of a wiring board. Thus, in the case of a BGA package, astructure usually is used which uses an organic carrier substrate.However, a wafer-state bonding to the carrier substrate causes thegeneration of a large strain proportional to the wafer size in a bondedarea around the wafer due to a difference in thermal expansion betweenthe carrier substrate and the Si wafer. The magnitude of the inducedstrain is proportional to the bonding temperature and inverselyproportional to the bump height. In the conventional bonding performedwith the use of solder, the soldering temperature during the packageassembly becomes inevitably high from the standpoint of solderingresistance in the mounting of the package to a wiring board, withconsequent increase in magnitude of the strain and a low solderstrength. For this reason, there arises a in problem that a large strainis induced in a soldered area around wafer, causing damage, when thework concerned is cooled to room temperature after bonding. On the otherhand, in the bonding structure using Au bumps, a bondable heatingtemperature in the prior art is 70° C. or higher from the standpoint ofimproving bondability by desorption and interfacial diffusion ofadsorbed molecules. At a low temperature of not higher than 200° C., alarge plastic deformation of Au bumps is essential to bonding. Thus, ithas so far been difficult to increase the shape after compressionbonding to 1/5 or more in terms of aspect ratio (height/diameter ratio).Particularly, at a bonding temperature of not higher than 130° C., theaspect ratio has been 1/10 or less and thus extremely low. Assuming thatthe bonding temperature is 70° C., a heat strain of the bonded productcan be roughly calculated as follows using a structure model shown inFIG. 19. In the case where the wafer size is 8 inches, the occurrence ofa deviation of 0.060 mm can be confirmed in a bump bonded-area aroundthe wafer on the basis of a difference between the thermal expansioncoefficient of Si, α=3×10⁻⁶/K, and that of a 108-6 carrier tapesubstrate, α=15×10⁻⁶/K. This deviation is absorbed by deformation of thebumps, deformation of the substrate and deformation of the Si wafer. Inthis case, a share of the strain taken up by the Si wafer and thecarrier substrate are calculated roughly from a stress balance. Young'smoduli of these components are Si:190 GPa, Au bump: 88 GPa, andpolyimide substrate:9 GPa. Since a sectional ratio is determined by thethickness of each component and a space volume ratio of the Au bumps, ifthe bump height is assumed to be H and a deviation in a verticalshearing direction of Au bumps is Δ, a main strain (ε) in a bump tensiledirection is represented as ε=((H²+A²)^(1/2)−H)/H in a two-dimensionalmodel and the relation between the bump height and the main strain isrepresented by such a curve as shown in FIG. 20. On the other hand, theelongation of Au bumps depends on the material and it is in the range of3% to 6% in the case of forming Au bumps by plating or ball bonding. Insuch a condition, when the main strain exceeds this value, there willoccur breakage of the Au bumps. More particularly, when the bondingtemperature is 70° C., even a bump having a sufficient bonding strengthis required to be 50 μm or more in bump height, and in the case of abonding temperature of 200° C., it is necessary that the bump height be80 μm or more. If the bonding strength between a chip or a substrate andAu bumps is low, it becomes necessary to ensure a much larger bumpheight. Therefore, when the Au bump height is set at a minimum heightnot causing breakage of Au bumps due to heat shrink after bonding, i.e.,50 μm at a bonding temperature of 70° C., the compression bond diameterbecomes 500 μm or larger; likewise, under the conditions of a bondingtemperature of 200° C. and a bump height of 80 μm, the compression bonddiameter becomes 400 μm or larger. Thus, taking variations incompression bond diameter and in shape into account, it has beendifficult to narrow the bump pitch to 500 μm or less.

SUMMARY OF THE INVENTION

[0010] It is an object of the present invention to provide asemiconductor package containing a semiconductor chip, such as anultra-multi-pin or high-speed LSI chip or the like, which is capable ofmaking the most of the chip performance and having an internalconnection with high heat resistance and high reliability. It is anotherobject of the present invention to provide a chip/substrate flip chipbonding method and apparatus which are capable of achieving alow-temperature process, mass-productivity and a high yield, which arerequired for realizing the semiconductor package stated above.

[0011] It is a further object of the present invention to provide amounting structure-in the case where a wafer-lebel mounting process iscarried out, which does not cause a problem of damage to a bondedportion due to heat strain in a cooling process after wafer-organiccarrier substrate bonding and which can diminish the bump pitch, as wellas a low cost wafer-stage package mounting method.

[0012] In the semiconductor package structure according to the presentinvention, an organic carrier substrate and a semiconductor chip arespaced apart 50 9 m or more, both are bonded in this state firmlymetallically through areawise arranged Au bumps as an intermediatematerial, and the gap therebetween is filled with resin. In the bondingmethod according to the present invention, a material constitution ofAu/Au is adopted for a flip chip bonded surface, the degree of cleannessof the said bonded surface is specified, and compression bonding isperformed under application of heat in a dry atmosphere having amoisture content of 100 Pa or less in terms of a partial pressure ofsteam or under scrubbing or application of a weak ultrasonicoscillation. This bonding method can afford the foregoing semiconductorpackage according to the present invention.

[0013] Results of studies made by the present inventors, which underliethe present invention, will be referred to below.

[0014] Generally, Au has a strength of 14 to 25 kg/mm² and does notundergo a work hardening, so its fatigue life is longer by one digit ormore than the solder, so if flip chip bonding using Au bumps can beperformed, the package will be improved in its temperature cyclereliability. However, it is necessary to considerably crush the Aubumps, or else it would be impossible to obtain a reliable bondedportion having a sufficient bonding strength. Consequently, there arisea problem of damage to the chip caused by a bonding load or ultrasonicoscillation and a problem that the filling of resin cannot be donesufficiently because the chip-to-substrate gap becomes too narrow. Thus,the application of Au bumps is difficult in a semiconductor packageusing an organic substrate. On the other hand, in the bonding of noblemetals such as Au and Ag, if the metal surfaces are made clean in anultra-high vacuum, it is possible to effect compression bonding whileminimizing the deformation of bumps under the conditions of a normaltemperature and a low load. However, for application to a massproduction line of semiconductor packages, there remains a problemconcerning a handling mechanism which effects registration of the chipand the substrate after cleaning in a vacuum and also in the processtact concerned. Thus, the application of the bonding method in questionto actual products is difficult from the point of view of both massproductivity and production cost. In more particular terms, this isbecause it is difficult to chuck the chip and the substrate in a vacuum,because the alignment mechanism is expensive if it is constituted usingan evacuatable material, and further because a high-speed operation in avacuum is apt to cause wear or seizure of the moving components, leadingto a shorter service life of the apparatus. If one could provide abonding method which can be carried out in atmospheric pressure andwhich is capable of affording bondability equal to that in a vacuum, itwill become possible to solve the abovementioned problem, facilitatehandling of the chip and the substrate, and operate various mechanicalportions at high speed.

[0015] On the basis of such a thought, we have made various studiesabout a clean surface state and a bonded state. FIG. 12 shows theresults of bonding performed by ultrasonic-bonding Au balls to an Audeposited film at a heating temperature of 100° C. in air and in anitrogen atmosphere. The bonding load was 50 g. In the same figure, anultrasonic output is plotted along the abscissa and a ratio of 16 g ormore in bonding strength is plotted along the ordinate. In bothatmospheres, the results of bonding shown therein are plotted as in thecase where the surface of the Au film is not treated and the case whereit has been cleaned by the ion radiation. An ultrasonic output whichaffords 100% successful bonding is 0 mW in a cleaned surface conditionand in a nitrogen atmosphere; that is, bonding could be done by the loadalone. In nitrogen, 100% bonding is reached at 1.4 mW even withoutcleaning. In contrast therewith, in the air, it is at 15 mW that 100%successful bonding is obtained even after surface cleaning, and a loadof 151 mW is required if cleaning is not performed. In other words,bonding in nitrogen for an uncleaned surface is superior in bondabilityto bonding in air for a cleaned surface. FIG. 13 shows the results ofhaving checked the degree of surface contamination by Auger analysis. Inthe case of an untreated sample, organic matter contamination or Scontamination is pronounced and Au concentration on the surface is aslow as 33 atom %. In contrast therewith, a sample which has beensubjected to a surface cleaning treatment is lower in contaminationlevel than the untreated sample, even when exposed to nitrogen or theatmosphere, and the Au concentration on the surface is at a high levelof 55 to 61 atom %. Thus, in Au/Au bonding, it is not only the surfacecontamination level which determines bondability thereof, but theinfluence of atmospheric gas is significant.

[0016] Next, therefore, for studying what atmospheric gas affectsbondability, gases contained in the atmosphere were analyzed and theinfluence on bondability of gases contained therein other than nitrogenwas studied. FIG. 14 shows a gas composition of the atmosphere (air).Oxygen and moisture are presumed to be gases which affect bondability.Therefore, we have prepared an atmosphere containing such gases,performed bonding therein and compared bondability. FIG. 15 shows theresults of bonding performed in an Ar gas atmosphere containing oxygenor moisture, bonding performed in air and bonding performed in nitrogenatmospheres. In the same figure, hatched areas represent ultrasonic waveoutput areas affording 100% successful bonding. It is seen that oxygenexerts no influence on bondability and that moisture exerts a badinfluence thereon. FIG. 16 shows a relation between the content ofmoisture in an atmospheric gas used and a minimum ultrasonic wave outputwhich affords 100% successful bonding. A correlation is clearlyrecognized between these two and an abrupt deterioration of bondabilityis recognized from a moisture content of 0.03 to 0.1 vol %. That is, ifthe moisture content in the atmosphere used is in the range of 0.03 to0.1 vol %, Au balls and Au pads can be bonded together to a bondingstrength of 16 g or higher by performing a surface cleaning treatmentand under low temperature and low load conditions of 100° C. and 50 g,respectively. From these results, it is apparent that in Au bonding thecontrol of moisture contained in the bonding atmosphere used is veryimportant. If the moisture is properly controlled, a sufficient bondingstrength is obtained by cleaning the Au bonding surface so as to become20 atom % or more in terms of the Au concentration thereof.

[0017] If this result is applied, then by combining the surface cleaningtreatment with a bonding method in a moisture-controlled atmosphere, achip formed with Au bumps can be bonded to Au pads or Au bumps on anorganic substrate of high strength while preventing deformation of thebumps under the conditions of a load not higher than 50 g per bump and abonding temperature of 100° C. to 200° C. In other words, by theapplication of surface cleaning and an Au bump/Au pad bonding method ina controlled atmosphere, it becomes possible to package anultra-multi-pin or high-speed LSI chip and make the most of the chipperformance: besides, it is possible to realize a package structurehaving a bonded portion with a high long-term reliability. Additionally,such a semiconductor package can be assembled with high massproductivity and high yield.

[0018] Semiconductor packages were assembled in accordance with thismethod and then subjected to reliability tests, the results of which areshown in FIGS. 17 and 18. FIG. 17 shows the results of a temperaturecycle test for packages having different Au bump heights, with chip sizebeing in the range of 5 to 10 mm square. It is apparent that the bumpheight and the breaking life are correlated with each other, and it iswhen the bump height is about 50 μm or more that the life exceeds apractically required life of 1,000 times. FIG. 18 shows the results ofhaving checked the relation between bump bonding strength and the rateof breakage occurrence in the case of repeated solder reflow. At a bumpstrength of 20 g, there is recognized the occurrence of breakage,although the probability thereof is small. Thus, from the standpoint ofpackage reliability, it is desirable that the bump height be 50 μm ormore and the bump strength 30 g or more.

[0019] The following description is now provided about bonding of acarrier substrate on a wafer level. By adopting the bonding methodaccording to the present invention, it is possible to effect bonding ata small crushing ratio, as shown in FIG. 21, at a bonding temperature of70° C. to 100° C. Strain between an Si wafer and a carrier substrate isabout 60 μm in model conditions shown in FIG. 19 and there is a bumpheight-main strain relation as shown in FIG. 20. If the bondingtemperature and bump height are set at 70° C. and 50 μm, respectively, amain strain becomes about 3% and a stress of 13 to 20 kg/mm² is induced.If the bonded interface strength of Au bumps is lower than this value,there will occur breakage at the interface, so it is necessary to obtaina sufficiently high bonding strength. In the prior art, a sufficientbonding strength is not obtained unless the bump crushing ratio isincreased to 50% or more, so that a bump diameter of 420 μm is requiredfor attaining a bump height of 50 μm, and thus it is difficult torealize a pitch of 500 μm or less. But, if a bonding method is adopted,which is carried out for cleaned surfaces in a dry atmosphere, bondingcan be done at a crushing ratio of 22% and an aspect ratio of 0.52, sothat it becomes possible to realize a bump height of 50 μm at acompression bond diameter of 100 μm. That is, it becomes possible toeffect a 200 μm-pitch bonding. Conversely, by setting the bump diameterand bump height at 200 μm and 100 μm, respectively, it is possible todiminish strain to 0.3% and an intra-bump induced stress is 2.6 kg/mm²,thus suppressing deformations to an elastic range of deformations, withno fear of damage to the bonded portion.

[0020] On the basis of the above studies, the present invention has beenaccomplished by providing a bonding method wherein consideration isgiven to the cleaning of the Au surface and to the amount of moisture ina bonding atmosphere, as will be described in detail later. Thefollowing novel semiconductor packages are obtained by the bondingmethod according to the present invention.

[0021] 1) A semiconductor package wherein electrode terminals of asemiconductor chip and internal connection terminals of an organicsubstrate are bonded together through Au bumps having a diameter of 300μm or less, a height of 50 μm or more and a height/diameter ratio of 1/5or more.

[0022] 2) A semiconductor package wherein a plurality of electrodeterminals of a semiconductor chip and a plurality of internal connectionterminals arranged on an organic substrate in a dimensionally identicalmanner with those electrode terminals are connected to each otherthrough Au bumps, and a plurality of external connection terminals ofthe organic substrate are constituted by solder bumps having a liquidphase temperature of 190° C. or higher.

[0023] 3) A semiconductor package wherein a semiconductor chip and aplurality of internal connection terminals on an organic substrate areflip chip-bonded through Au bumps with a pitch of 400 μm or less, anarea of external connection terminals and that of internal connectionterminals on the organic substrate are divided by slits, and theexternal and internal connection terminals are connected to each otherthrough wires extending through the slits.

[0024] 4) A semiconductor package wherein a semiconductor chip and aplurality of internal connection terminals arranged areawise on anorganic substrate are bonded together in a facedown manner through Aubumps, and an area of internal connection terminals and that of externalconnection terminals overlap each other on a projection surface.

[0025] 5) A semiconductor package wherein a plurality of semiconductorchips having electrode terminals and arranged at intervals of 1 mm orless and a plurality of internal connection terminals on an organicsubstrate are connected to each other through Au bumps, and externalconnection terminals of the organic substrate are constituted by solderbumps having a liquid phase temperature of 190° C. or higher.

[0026] In each of the above semiconductor packages, it is preferablethat resin be filled between the semiconductor chip and the organicsubstrate.

BRIEF DESCRIPTION OF THE DRAWINGS

[0027]FIG. 1 is a sectional view of a semiconductor package according tothe present invention.

[0028]FIGS. 2A and 2B are diagrams showing Au bump shapes.

[0029]FIG. 3 is a sectional view of a semiconductor package according tothe present invention.

[0030]FIG. 4 is a sectional view of a semiconductor package according tothe present invention.

[0031]FIG. 5 is a plan view of an organic carrier substrate to be usedin the semiconductor package of FIG. 4.

[0032]FIG. 6 is a sectional view of a multi-tip semiconductor packageaccording to the present invention.

[0033]FIG. 7 is a process flow diagram of a bonding procedure adopted toa chip-carrier substrate bonding method according to the presentinvention.

[0034]FIG. 8 is a diagram of a system configuration for realizing thebonding method illustrated in FIG. 7;

[0035]FIG. 9 is a process flow diagram of a bonding procedure adopted toa chip-carrier substrate bonding method according to the presentinvention.

[0036]FIG. 10 is a diagram of a system for realizing the bonding methodillustrated in FIG. 9.

[0037]FIG. 11 is a diagram of a system including the pretreatmentchamber and the bonding chamber illustrated in FIG. 10.

[0038]FIG. 12 is a graph which shows test results indicating how abonding atmosphere of nitrogen and that of air exert an influence onbonding results.

[0039]FIG. 13 is a graph which shows the results of Auger analysis whichindicating to what degree bonding surfaces are contaminated.

[0040]FIG. 14 is a table which shows a gas composition of an airatmosphere.

[0041]FIG. 15 is a bar graph which shows experimental results whichindicate how various bonding atmospheres exert an influence on bondingresults.

[0042]FIG. 16 is a graph which shows experimental results indicating howthe moisture content of a bonding atmosphere exerts an influence onbonding results.

[0043]FIG. 17 is a graph which shows the results of a temperature cycletest conducted for semiconductor packages according to the presentinvention.

[0044]FIG. 18 is a graph which shows the results of a solder reflowrepeating test conducted for semiconductor packages according to thepresent invention.

[0045]FIG. 19 is a diagram of a semiconductor package model.

[0046]FIG. 20 is a graph which shows a height-strain relation of a bump.

[0047]FIG. 21 is a graph which shows a ratio of crushing-bondingstrength relation.

BEST MODE FOR CARRYING OUT THE INVENTION

[0048] Embodiments of the present invention will be described below indetail with reference to the accompanying drawings.

[0049]FIG. 1 shows a sectional view of a structure of a semiconductorpackage according to the present invention. In the same figure, Au bumps7 are formed by ball bonding on Al or Au electrode pads 2 formed on asemiconductor chip 1 (hereinafter referred to as the “chip 1”). Anorganic carrier substrate comprises an organic insulating plate 3,internal connection terminals 4 formed on one surface of the organicinsulating plate 3, external connection terminals 5 formed on a surfaceopposite to the surface side of the organic insulating plate 3, and aplated resist 6 which covers the surface of the insulating plate aroundthe external connection terminals 5. The internal and externalconnection terminals 4 and 5 are formed by a method wherein etching isperformed through Cu plating or Cu foil. Those terminals areelectrically interconnected through through-holes, and wiring formed inthe organic substrate 3 and their outermost surfaces are plated with Auafter Ni or Pd plating as an undercoat. The assembly of the package iscarried out in the following manner. Au bumps 8 are formed on theinternal connection terminals 4 of the carrier substrate by ball bondingand are then aligned with the Au bumps 6 of the chip 1 so that both Aubumps come into contact with each other, the surrounding atmosphere isevacuated to 1 Pa or less, followed by heating to a temperature of 150°C. to 250° C. to effect compression bonding. The load applied is 30 to80 g/bump and a displacement quantity control is carried out during thebonding work to prevent the bumps from being excessively crushed.

[0050]FIGS. 2A and 2B show initial shapes of Au bumps formed by ballbonding, in which a chip-side ball bump shape FIG. 2A is obtained bysuitably selecting discharge and bonding conditions and a capillary toolshape so that the compression bond diameter Dc is 110±10 μm, theshoulder height Hc with which a tip end face of the capillary tool hasbeen in contact is 25±5 μm, the diameter Dh of a central swollen portionof each bump is 50 μm, and the height Hh of that portion is 50±10 μm. Abonding strength of 80 g or more in terms of shear strength is obtained.On the other hand, a substrate-side ball bump shape FIG. 2B is obtainedby making the deformation of the ball smaller than that on the chip sideand adopting a shoulder height-Hk of 40±10 μm, which is higher than thatof the chip side. In this ball bonding, the bonding terminal surface ofthe substrate is subjected to sputter cleaning just before bonding witha view to improving bondability. A bonding strength of 50 g or more isobtained in terms of shear strength. Both bumps are compression-bondedtogether while controlling the amount of the bumps to be crushed by adisplacement quantity control so that the bumps are bonded metallicallywith each other at the respective central swollen portions. In a bumpcolumn resulting from the bonding, the bonded interface portion betweenboth vertically adjacent bumps in the figure is the most constrictedportion. Also, in point of strength, the bonded interface portion is thelowest. As to the height H between the chip and the substrate aftercompression bonding, there is obtained a height H of about 70±10 μm.Thereafter, the compression-bonded product is taken out into theatmosphere, a dam 19 is formed on the substrate, then resin 9 superiorin fluidity is poured and cured, and lastly solder bumps 10 are formedon the external connection terminals to complete a package.

[0051] The following effects are obtained by this embodiment. 1) SinceAl electrode pads of the chip and the internal connection terminals ofthe organic carrier substrate are connected to each other by a flip chipbonding method, the pads can be arranged areawise and the pad pitch canbe moderated, even in the case of a multi-pin LST chip, thus permittingthe chip to be mounted onto a semiconductor package. 2) Because of thestructure wherein the chip and the organic carrier substrate areelectrically connected to each other over the shortest distance, apackage of a high transmission speed can be constituted, which packagecan make the most of the performance of a high-speed processing LSIchip. 3) Since the chip-to-substrate bonded distance is 50 μm or more,the strain induced in each Au bump column is diminished. 4) Because ofthe structure wherein the strain induced by a difference in thermalexpansion between the chip and the substrate is absorbed at the centralpart of the Au bump column, a high-stress is not applied to the weakestAl pad/Au bump bonded interface. 5) Au is higher in strength and longerin fatigue life than solder, and the temperature cycle life of thebonded portion in the package is long. 6) When the package is mounted ona printed wiring board, a large heat strain is not developed on thesolder bumps which bond the two with each other because the externalconnection terminals are formed on the organic carrier substrate havingthe same thermal expansion coefficient as that of the wiring board. 7)Because of the above effects 3) to 6), the temperature cycle reliabilityof the internal and external bonded portions in the package becomesextremely high. Moreover, by the adoption of a new bonding/assemblingprocess, it becomes possible to effect a high-strength bonding in asmall bonding load condition, so that the likelihood of chip damage inthe bonding process decreases and it is possible to realize a mountingprocess which is capable of affording a high yield. That is, anultra-multi-pin high-speed LSI chip can be mounted to a highly reliablesemiconductor package affording high yield without deteriorating theperformance.

[0052] Further, according to this embodiment, since the connection iscompleted in a chip projection area and in a face-down bonding manner, aplurality of chips can be mounted in proximity to one another.Consequently, in a multi-chip package, the package size can be reducedconsiderably. Besides, since the heat resistance of the intrapackagebonded portion is the same as that of a package based on theconventional Au wire bonding technique, the same solder reflow processas in the prior art can be adopted for mounting the package to a wiringboard.

[0053]FIG. 3 shows another example of a sectional view of a structure ofa semiconductor package according to the present invention. In the samefigure, as an organic carrier substrate there is used a tape substratecomprising a polyimide tape 13 having apertures and combinedinternal-external connection terminals 14, the terminals 14 having beensubjected to patterning, and each is formed by a surface and a back ofthe same Cu land. On each side of each connecting terminal, Ni platingis applied as an undercoat and Au plating is applied to the outermostsurface. On the aperture-side, internal connection terminals are formedAu bumps 16, which are bonded to Au bumps 15 formed on Al or Auelectrodes 12 of an LSI chip 11. The Au bump bonding is performed in thefollowing manner. First, the substrate-side Au bump surfaces are cleanedby Ar ion sputtering and the substrate is fed into a bonding chamberwhich is hermetically sealed without exposure to the air and which isheld in a dry atmosphere at a partial pressure of steam of not higherthan 100 Pa. The chip formed with Au bumps is heated in a vacuumchamber, allowing adsorbed water to be desorbed, and is then fed intothe bonding chamber. In the bonding chamber, the Au bumps on thesubstrate side and the Au bumps on the chip side are aligned with eachother and the chip is mounted on the substrate while facing down,followed by the application of heat and pressure from the chip side withuse of a bonding tool, and bonding is carried out by scrubbing severaltimes at an amplitude of 5 to 10 μm or by ultrasonic oscillation. Atthis time, by deformation control, the Au bumps are prevented from beingexcessively crushed and a chip-to-substrate gap of 50 μm or more isensured. Resin 17 is filled and cured in the gap between the chip andthe substrate and thereafter solder bumps 18 free of lead and having aliquid phase temperature of 190° C. to 230° C. are formed on theexternal connection terminals of the substrate. This package is designedso that the chip and the substrate are of the same size.

[0054] According to this embodiment, for the same reason as that in theembodiment of FIG. 1, an ultra-high speed processing LSI chip can bemounted to a small-sized package without deteriorating itscharacteristics. Moreover, there is obtained an effect such that, whenthe package is mounted on a wiring board at the same time, a long-termreliability of inner and outer bonded portions of the package can berendered extremely high. There also is obtained an effect such that thesize of a multi-chip package can be reduced to a great extent.

[0055] Further, in this embodiment, the size of the chip and that of thetape substrate are the same and all the bonded portions on a projectionsurface are accommodated inside the chip surface. Therefore, if aplurality of semiconductor integrated circuit devices (say, LSI) havingAu bumps are formed on a single Si wafer and this wafer is mounted on atape substrate with patterns for plural packages formed thereon,followed by separation by cutting in the final process after theformation of solder bumps, then it becomes possible to assemble aplurality of chip-size packages at a time, and hence, it is possible togreatly reduce the manufacturing cost. The manufacturing method is thesame as that used in the embodiment of FIG. 1.

[0056] This embodiment is suitable for a case where the number of pinsis not larger than 200.

[0057]FIG. 4 shows a further example of a sectional view of a structureof a semiconductor package according to the present invention and FIG. 5is a plan view of an organic carrier substrate used in FIG. 4. Theorganic carrier substrate is a tape substrate comprising a polyimidetape 23 and an etched Cu foil pattern bonded to the tape. The polyimidetape has an external connection terminal portion and apertures formedalong a boundary between an internal connection terminal area 24 and anexternal connection terminal area 25. The latter apertures are formed asslits 29, which slits are each of a size not permitting transmission ofa tape strain in the internal connection area to the external connectionarea. The Cu foil pattern comprises internal and external connectionterminals 26 and 27 and wiring portions 28 passing through the slits 29.The internal connection terminals 26, which are plated with Au on thetape substrate, and Au bumps 30 formed on electrode terminals 22 of achip 21 are bonded together metallically. According to the bondingmethod adopted herein, first the surfaces of the internal connectionterminals on the tape substrate are cleaned by sputtering with Ar ions,then the chip is mounted on the substrate while positioning it in a dryatmosphere of not higher than 100 Pa as a partial pressure of steam,then the entire temperature is raised to 200° C. by heating, andcompression bonding is carried out by the application of pressure andultrasonic oscillation from the chip side. A reinforcing plate 31 havinga thermal expansion coefficient equal to that of the wiring board whichis for mounting the package thereon, is affixed with an adhesive 32 tothe chip mounted side in the external connection terminal area. A highlyfluid resin 33 is poured and cured between the chip and the substrate.When the resin is poured, a backup member is used to prevent leakage ofthe resin from the slit portions 29, which slit portions are also filledwith the resin to be cured. Thus, the wiring passing through the slitsare covered and protected with the resin.

[0058] According to this embodiment, an ultra-multi-pin LSI chip having150 pins or more as the number of electrode terminals can be bondedsecurely to the terminals of the tape substrate by a flip chip bondingmethod using a high melting material having a long fatigue life and ahigh resistance to environment. Consequently, an ultra-multi-pin andultra-high speed processing LSI chip can be assembled to a plasticpackage of low cost and high reliability in a mounted state on a wiringboard. When the package according to this embodiment is mounted on awiring board, a heat strain induced by a difference in thermal expansionbetween the chip and the carrier substrate is shut off by the slitportions and the thermal expansion coefficient of the externalconnection terminal area becomes approximately equal to that of thewiring board. Therefore, a large thermal stress is not developed in thesolder bump connections and the temperature cycle life of the solderbump connections becomes very long.

[0059]FIG. 6 shows an example of a sectional view of a structure of amulti-chip package according to the present invention wherein aplurality of chips are arranged close to one another at intervals of 1mm or less. In the same figure, internal connection terminals 44,external connection terminals 45 and wiring patterns are formed on bothsurfaces of a module substrate 43. A thick Ni plating 47 is applied asan undercoat to the internal connection terminals and Au plating 48 isapplied onto the undercoat to form Au bumps. On Al electrode pads 42 ofa chip 41 are formed Au stud bumps 46 by a wire bonding method. The Aubumps on the substrate side and those on the chip side are bondedtogether in the following manner. The surfaces of the Au bumps on thesubstrate side are cleaned by sputter cleaning, then the Au bumps thuscleaned are fed into a bonding chamber sealed hermetically withoutexposure to the air and filled with a dry atmospheric gas, while thechip-side Au bumps are heat-treated in a vacuum to remove adsorbed waterand organic matter, then both bumps are aligned, opposed to each other,and bonded together by the application of heat, pressure and scrubbingoscillation. A plurality of chips are bonded to the module substrate andresin 49 is filled between the chip and the substrate. On the back ofthe module substrate are formed solder bumps 50 having a liquid phasetemperature of 190° C. or higher for connection with a mother board. Asan external connecting mechanism there may be adopted a structurewherein the solder bumps are replaced by lead terminals and the leadterminals are soldered to a mother board.

[0060] In this embodiment, since the module substrate-chip connectionportion comprises a metallic bonding of highly strong Au bumps with eachother, the temperature cycle reliability of the internal connection ishigh and there are no restrictions on the heating temperature at thetime of soldering to a mother board because the bonded portion has heatresistance. Moreover, chips can be mounted on the module substrate inclose proximity to one another to such a degree that adjacent chips arein contact with each other, thus permitting the module size to bereduced to a minimum.

[0061]FIG. 7 shows a bonding procedure adopted in the bonding methodaccording to the present invention. Au bumps formed by a ball wirebonding method are high in the purity of Au as bump material and aresoft, and therefore, they can be formed in a step just before flip chipbonding. For this reason the degree of cleanness of the bump surfaces ishigh. Consequently, it is possible to omit the surface cleaningtreatment for both bumps. Chips are mounted on the carrier substrate atatmospheric pressure while being aligned, then in this state, theambient atmosphere is evacuated to 100 Pa or less, followed by heating,allowing moisture and organic matter adsorbed on the bump surfaces to bedesorbed, and then compression bonding is performed. At this time, ifscrubbing is performed plural times together with pressing at anamplitude of several μm to ten odd μm or if ultrasonic oscillation isapplied, it is possible to improve the bonding strength easily. Thepositioning of the chips is performed in the air while setting thesubstrate and the chips to the bonding system. After the positioning, aload of several grams or less per bump is applied to each of the chipswith use of a pressing jig. In this way, it is possible to prevent theoccurrence of a positional deviation between the chips and the substrateduring the pressing and to expose the bonding area to a vacuumatmosphere as large as possible, thereby allowing adsorbed matters to bedesorbed. After the bonding, the substrate with chips is taken out intothe air, a liquid resin is penetrated between the chips and thesubstrate, and then, after the removal of air bubbles, the resin iscured by heating. Thereafter, flux is applied to the Au-plated externalconnection terminals on the back of the carrier substrate, solder ballsare mounted thereon, and the solder is allowed to reflow by heating toform solder bumps. In the case where a plurality of packages areassembled using a single substrate, there is provided, as a final step,a cutting step for cutting off the packages from each other. Theassembling process is now completed.

[0062]FIG. 8 shows an example of a bonding system for realizing thebonding method illustrated in FIG. 7. In FIG. 8, an upper chamber 54 anda lower chamber 51, which are for evacuation, are in close contact witheach other through an O-ring 61. A combined pressing jig and vacuumflange 55 for pressing chips 68 is integral with a central part of theupper chamber 54 in a hermetically sealed manner through bellows 56.Above the flange is disposed with a cylinder 62 which is fixed to asupport arm 53, and a piston 75 of the cylinder 62 is secured to theflange to control vertical movements of the flange. The upper chambercan move up and down independently of the movement of the flange and iscontrolled by a drive mechanism 63 attached to the support arm. Therelative moving distance of the upper chamber and the flange is designedto be 20 mm or more. According to this structure, while a low load isapplied to the semiconductor chips 68 by the flange, the upper chamberis pulled up, thereby permitting a position checking camera to beinserted into the chamber. A heat stage 57 for supplying and setting thesemiconductor chips 68 and a carrier substrate 700 in a contacted stateof Au bumps 69 and Au pads 71 is internally provided with a heater 60and is further provided with a stage driving mechanism 59 for drivingthe stage right and left slightly. The heat stage is supported by meansof a bearing 58 which functions to bear the movement of the heat stageand also bear the bonding load. The size of a space to be evacuated isdesigned to be a minimum size which permits the chips and the substrateto be received therein, and an evacuating pump 64 is selected so thatthe time required for evacuation to 10⁻² torr or lower is not longerthan 20 seconds. N₂ gas is used as a leakage gas for releasing thechamber pressure to the atmospheric pressure.

[0063] Since this embodiment is of a structure wherein the bondingmechanism is disposed outside the vacuum chamber and only thesurroundings of a bonding sample can be evacuated, the time required,from the positioning under atmospheric pressure until obtaining a vacuumatmosphere necessary for the bonding, is shortened to a large extent,and a single bonding process comprising substrate-chipregistration→evacuation→compression bonding→leak to the air can be donewithin one minute, thus making it possible to apply the bonding methodaccording to the present invention to mass production. Besides, sincescrubbing of several μm or so can be performed from the substrate sidein the compression bonding step, it becomes possible to enhance thebonding strength at a low load and hence possible to further diminishthe likelihood of chip damage.

[0064]FIG. 9 shows another bonding procedure used in the bonding methodaccording to the present invention. If Au pads or Au bumps formed byplating are formed thicker than several μm, an increase of cost results,so it is necessary to form them to a thickness of not larger than 1 μm.On the other hand, if Au plating is thin, the deformation of Au padsbecomes very small and therefore the surface contamination level exertsa great influence on the bonding. In the illustrated procedure,therefore, there are performed a treatment of cleaning the surfaces ofthe substrate-side Au pads by sputter cleaning and a treatment ofheating the chip-side Au bump surfaces in a vacuum only to remove theadsorbed water. After performing both treatments, the components areintroduced into a hermetically sealed chamber held at a gas pressure of5×10³ to 2×10⁵ Pa or more and in a dry air atmosphere of 100 Pa or lessas a partial pressure of steam in a contactless state with theatmosphere or in a gaseous atmosphere consisting mainly of N₂ or Ar, thesubstrate is put on the heat stage, while the chips are chucked on thepressing jig by vacuum suction, and then the substrate and the chips arealigned with each other and subjected to compression bonding underscrubbing or ultrasonic oscillation. In the case where the substrateused is composed of patterns corresponding to plural packages, chips arefed successively for bonding. After the bonding, the module thusobtained is taken out into the atmosphere, then resin is filled betweenthe chips and the substrate and is cured, solder bumps are formed on thesubstrate-side external connection terminals, followed by cutting intothe plural packages. The assembling work is now completed.

[0065]FIG. 10 shows an example of a bonding system for realizing thebonding method illustrated in FIG. 9. The bonding system basicallycomprises a pretreatment chamber 81 for cleaning pad surfaces of asubstrate; a chip supply chamber 83 for heat-treating a semiconductorchip in a vacuum and supplying it to a bonding chamber about to bedescribed; a bonding chamber 82 for aligning the substrate and the chipwith each other and for bonding the two under the application of heatand pressure and under conditions of scrubbing or ultrasonicoscillation; a substrate discharge chamber 86 for taking out thesubstrate with the chip from the bonding chamber; a dry gas supplymechanism 85 for supplying a dry gas to the pretreatment chamber,bonding chamber, chip supply chamber and substrate discharge chamber,each of which are hermetically sealed; an evacuating system 84 forevacuating each of those chambers; and a substrate supply mechanism 87for supplying a substrate to the pretreatment chamber. Those chambersare interconnected through gate valves 88, 89 and 90 and a substrate ora chip is conveyed through the chambers. As the dry gas there may beused any gas irrespective of whether it is an oxidizing gas or anon-oxidizing gas insofar as it is not higher than 100 Pa as a partialpressure of steam. Examples are air, nitrogen and argon.

[0066]FIG. 11 shows an example of the pretreatment chamber and of thebonding chamber both illustrated in FIG. 10. In the pretreatment chamber100 there is provided a mechanism for sputtering a carrier substrate 129with Ar ions. A cathode electrode 107 is disposed in an electricallyinsulated manner from the system through an insulating member 108. Abovethe cathode electrode 107 there is disposed an anode electrode 106,which is at the same potential as the ground potential. After thesubstrate is set onto the cathode electrode and the interior of thechamber is evacuated, Ar gas is introduced and a high-frequency voltagewith a direct current component interposed thereon is applied betweenthe electrodes from a high frequency generator 109, allowing a glowdischarge to be generated between the electrodes. At this time, Ar gasis ionized and is accelerated toward the substrate by a DC voltagecomponent, whereby the substrate surface is etched physically andcleaned. After the cleaning, nitrogen gas is introduced up to the samegas pressure as in the next bonding chamber 116. In the bonding chamberthere are mounted a substrate conveying mechanism 127, an alignmentmechanism comprising a camera 125, a drive system 126 for the camera, anXY moving stage 124, a controller 123, a bonding mechanism comprising apressing mechanism 118, a support arm 121, an ultrasonic oscillationmechanism 119, a bonding tool 120, a controller 122, and a chip supplymechanism which conveys a chip 131 to a bonding tool, though not shown.The bonding chamber is first evacuated while the system is in operation,and a dry nitrogen gas is introduced therein up to near the atmosphericpressure to maintain the interior of the chamber in a dry atmosphere atatmospheric pressure. A substrate 130 is mounted on a heat stage 128 inwhich is incorporated a heating mechanism. The chip 131 is chucked tothe bonding tool by vacuum suction. The camera is inserted between thechip and the substrate to check the position of Au bumps on the chip andthat of Au pads on the substrate while alignment is made by the XYmoving stage. Then after movement of the camera, the chip is moveddownward by the pressing mechanism, and bonding is performed under theapplication of pressure and ultrasonic wave.

[0067] According to this embodiment, even if the Au pads assubstrate-side internal connection terminals are, contaminated withorganic matter or with an oxidizing metal due to diffusion from theundercoat, since their surfaces are physically etched with Ar ions andcleaned, their bondability to the chip-side Au bumps is greatly improvedand a highly reliable bonded portion of high strength is obtained.Besides, since the bonding chamber is kept in a dry nitrogen gasatmosphere at atmospheric pressure having a reduced moisture content,the bondability is not deteriorated, the chip can be chucked by vacuumsuction, and the moving components in the drive system can be used overa long service life without causing seizure. Therefore, it is possibleto realize a process and system capable of mass production and able toattain a highly reliable chip-carrier substrate bonding. Thus, even inthe case of an ultra-multi-pin and ultra-high speed LSI chip withelectrode pads arranged areawise thereon, the chip and the organiccarrier substrate can be bonded together directly and with a highstrength through Au bumps. In this way it is possible to obtain a highlyreliable semiconductor package at low cost without deteriorating thechip performance.

[0068] According to the present invention, as set forth above, anultra-multi-pin or high-speed LSI chip can be packaged compactly and thechip performance can be enhanced to the utmost. Moreover, with use of anorganic carrier substrate of low cost, it is possible to provide asemiconductor package which is highly reliable in its connections.Further, it is possible to provide an Au bump/Au pad or Au bump/Au bumpflip chip bonding method capable of fabricating a semiconductor packagethrough a highly mass-producible process, as well as a bonding systemfor realizing the said method.

1. A semiconductor package characterized in that it comprises: a semiconductor chip having electrode terminals; an organic substrate having internal connection terminals connected to said electrode terminals; and a resin filled between said semiconductor chip and said organic substrate, wherein said electrode terminals and said internal connection terminals are bonded together through Au bumps each having a diameter of not larger than 300 μm height of not smaller than 50 μm and a height/diameter ratio of not lower than 1/5.
 2. A semiconductor package according to claim 1, characterized in that it has a bonding strength of not lower than 30 g in terms of a tensile breaking strength per bump.
 3. A semiconductor package characterized in that it comprises: a semiconductor chip having a plurality of electrode terminals; an organic substrate having a plurality of internal connection terminals and a plurality of external connection terminals, said internal connection terminals being arranged dimensionally in the same manner as with said electrode terminals and connected to the electrode terminals through Au bumps, and said external connection terminals being constituted by solder bumps having a liquid phase temperature of not lower than 190° C.; and a resin filled between said semiconductor chip and said organic substrate.
 4. A semiconductor package characterized in that it comprises: a semiconductor chip; an organic substrate having a plurality of external connection terminals and a plurality of internal connection terminals which are flip chip-bonded to said semiconductor chip through Au bumps with a pitch of not larger than 400 μm, the area of said external connection terminals and that of said internal connection terminals being divided from each other through slits, and said external connection terminals and said internal connection terminals being connected to each other through wiring which passes through said slits; and a resin which is filled between said semiconductor chip and said organic substrate and which covers said wiring.
 5. A semiconductor package characterized in that it comprises: a semiconductor chip; an organic substrate having a plurality of internal connection terminals arranged areawise and bonded in a face-down manner to said semiconductor chip and a plurality of external connection terminals arranged areawise, the area of said internal connection terminals and that of said external connection terminals overlapping each other on a projection surface; and a resin filled between said semiconductor chip and said organic substrate.
 6. A semiconductor package according to claim 5, characterized in that a pair of said internal connection terminal and said external connection terminal are formed on a back and a surface of a single Cu land.
 7. A semiconductor package characterized in that it comprises: a plurality of semiconductor chips having electrode terminals and arranged at intervals of not larger than 1 mm; an organic substrate having a plurality of internal connection terminals connected to said electrode terminals through Au bumps and a plurality of external electrode terminals constituted by solder bumps having a liquid phase temperature of not lower than 190° C.; and a resin filled between said semiconductor chips and said organic substrate.
 8. A flip chip bonding method for an organic substrate and a semiconductor chip, characterized in that it comprises the steps of: forming Au bumps on electrode terminals of the semiconductor chip, forming an Au plating layer on surfaces of internal connection terminals of an organic carrier substrate or a tape substrate, subjecting Au bonding surfaces of a substrate-side bonding portion and of a chip-side bonding portion to a cleaning treatment so as to give an Au concentration of not lower than 20 atom %, and compression-bonding said surfaces in a dry atmosphere of not higher than 100 Pa as a partial pressure of steam without exposure to the atmosphere and under the application of heat and pressure.
 9. A flip chip bonding method according to claim 8, characterized in that said cleaning treatment for the substrate-side bonding portion is sputter cleaning using Ar ions, the bonding atmosphere is at a partial pressure of steam of not higher than 100 Pa and comprises a gas consisting principally of air, nitrogen, or Ar having a pressure of 5×10³ to 2×10⁵ Pa, and the compression bonding is carried out with scrubbing or ultrasonic oscillation simultaneously with the application of heat and pressure.
 10. A flip chip bonding method for an organic substrate and a semiconductor chip characterized in that it comprises the steps of: forming Au bumps on electrode terminals of the semiconductor chip and on internal connection terminals of an organic carrier substrate or a tape substrate by an Au ball bonding method, aligning the Au bumps of a substrate-side bonding portion and the Au bumps of a chip-side bonding portion with each other under atmospheric pressure, forming a hermetically sealed space in that state or conveying the substrate and the chip after registration into a hermetically sealed chamber, evacuating said hermetically sealed chamber until there is obtained a bonding atmosphere of not higher than 100 Pa, and compression-bonding the substrate and the chip under the application of heat and pressure or with scrubbing or ultrasonic oscillation simultaneously with the application of heat and pressure.
 11. A flip chip bonding system characterized in that it comprises: a hermetically sealed pretreatment chamber for cleaning surfaces of Au pads formed on a substrate; a hermetically sealed bonding chamber for compression-bonding the Au pads on the substrate and Au bumps formed on a semiconductor chip with each other under the application of heat and with scrubbing or ultrasonic oscillation while maintaining a dry atmosphere; a hermetically sealed chip supply chamber for supplying the semiconductor chip with Au bumps to said bonding chamber; and a hermetically sealed discharge chamber for taking out the thus-bonded semiconductor chip and substrate into the atmosphere, wherein said pretreatment chamber and said bonding chamber, said bonding chamber and said chip supply chamber, and said bonding chamber and said discharge chamber are respectively connected through gate valves.
 12. A flip chip bonding system characterized in that it comprises: a bonding mechanism for the application of pressure and heat; a supply mechanism for supplying a substrate and a semiconductor chip to said bonding mechanism; a hermetically sealed vessel in which said semiconductor chip and said substrate are set; and an evacuating mechanism, said hermetically sealed vessel being divided into an upper vessel and a lower vessel, said upper vessel comprising a component connected to a pressing mechanism and a component contacted closely with said lower vessel through an O-ring, both components being joined together in a hermetically sealed manner through a relatively movable bellows.
 13. A semiconductor package fabricating method characterized in that it comprises the steps of: subjecting a semiconductor wafer formed with a plurality of semiconductor integrated circuit devices having Au bumps and an organic substrate for a plurality of packages formed with Au bumps or Au pads to a surface cleaning treatment; thereafter compression-bonding a semiconductor wafer and said organic substrate with each other under the application of heat and with scrubbing or ultrasonic oscillation; pouring and curing a resin between said semiconductor wafer and said organic substrate; subsequently forming solder bumps on external connection terminals of said organic substrate; and thereafter assembling a plurality of chip-size packages by a cutting operation. 